About
Muhsin Celik was born and grew up in Ankara, Turkey. His interest in science and technology guided him to Ankara Science High School which was the first science high school in Turkey and originally funded by the Ford Foundation. After receiving his Electrical and Electronics Engineering degree from Middle East Technical University in Ankara, he came to the USA for graduate studies. He completed his M.S. and Ph.D. in Electrical Engineering at North Carolina State University in 1998 and moved to Austin, TX to join Motorola Advanced Products Research and Development Labs. He worked on the transistor technology development for PowerPC High Performance applications in Austin before working in Grenoble, France as an international expatriate with Freescale Semiconductor. Muhsin's industrial experience continued back in the USA with a variety of leadership positions at Freescale Semiconductor and later, STMicroelectronics. He worked at the IBM International Semiconductor Development Alliance in Fishkill, NY and later became the STMicroelectronics Project Leader at SUNY Nanotech in Albany, NY. Subsequently, Muhsin joined GlobalFoundries in 2015 and served as Senior Director at the Fab 8 site located in Saratoga County, NY. In GF, he led the 14nm FINFET program, and held various executive positions for fab expansions, business operations and transformation. He served on the Industrial Advisory Board of CNSE, SUNY Poly. He is an IEEE senior member.
Ph.D., Electrical Engineering, minor in Solid State Physics, North Carolina State University
Thesis: In-situ Surface Cleaning Prior to Si Selective Epitaxy in UHV-RTCVD System
Areas of graduate study: Microelectronics, solid state devices and physics, surface physics, VLSI design
M.S., Electrical Engineering, North Carolina State University
B.S., Electrical and Electronics Engineering, Middle East Technical University
Research
Teaching
ECSE 2210: Microelectronics Technology
ECSE 4220: VLSI Design
ECSE 4250: IC Process and Design
ECSE 4961/6961: Fab Technology Semiconductor Mfg
ECSE 4900: Multidisciplinary Capstone Design
Publications
“Tunneling Field Effect Transistor (TFET) Having a Semiconductor Fin Structure.” US PTO No: 0322479 issued on 11/3/2016.
“Separately strained N-channel and P-channel transistors”. US PTO No:7041576 issued on 5/9/2006. Also filed as an International Patent.
“A 10nm platform technology for low power and high-performance application featuring FINFET devices with multi work function gate stack on bulk and SOI” Seo, K. et al. 2014 Symp. on VLSI Technology Digest of Technical Papers, Pages: 14-15.
“14nm FDSOI technology for high speed and energy efficient application” Weber O et al. 2014 Symposium on VLSI Technology Digest of Technical Papers, Pages: 16-17.
“High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond” Liu, Q. et al. 2013
International Electron Devices Meeting Digest of Technical Papers. Pages: 9.2.1-4.
“High performance bulk planar 20nm CMOS technology for low power mobile applications” Shang H. et al. 2012 Symposium on VLSI Technology Digest of Technical Papers, Pages: 129-130.
“New layout dependency in high-k/Metal Gate MOSFETs” Hamaguchi, M et al. 2012 International Electron Devices Meeting Digest of Technical Papers. Pages 25.6.1-4.
“Novel High-Performance Analog Devices for Advanced Low-Power High-k Metal Gate Complementary Metal-Oxide-Semiconductor Technology”, Han, J. et al. Japanese Journal of Applied Physics, Volume 50, Number 4S.
“Application of On-Chip MIM Decoupling Capacitor for 90nm SOI Microprocessor” Roberts R et al. 2005 International Electron Devices Meeting, Digest of Technical papers Pages: 72-75.
“A 45 nm gate length high performance SOI transistor for 100 nm CMOS technology applications”, Celik, M et al. 2002 Symposium on VLSI Technology. Digest of Technical Papers. Pages: 166-167.